The present invention relates to a bit field operational arithmetic unit and to an operating method as what is effectively applicable to an integer arithmetic unit of a processor.
Bit field operations include, for instance, a process of extracting or replacing an optional area of data. An extract instruction, for instance, is intended to designate the extraction of an optional area of data. In response to the extract instruction, processes shown in FIG. 16 are basically performed. More specifically, (i) a data shift process for shifting an area to be extracted to the rightmost end of the data, (ii) a mask data generating process for generating mask data with "1" set for a bit corresponding to each bit in the area to be extracted, and (iii) an expansion process for fetching only an area whose bit value is 1 out of the mask data and filling the remaining area with 0 or sign bits. To be concrete, No. h bit of input data is shifted in right alignment and any area other than what is defined by area width LEN is expanded with the sign bit S or by filling it with bit 0 to obtain output data with the desired area LEN extracted from the input data. The area to be subjected to sign expansion or 0-expansion is designated by the mask data. A deposit instruction, for instance, is intended to designate the process of replacing the latter. Under this instruction, the processes shown in FIG. 17 are basically performed. More specifically, (i) a data shift process for shifting an area to be replaced to the left up to a position of replacement, (ii) a mask data generating process for generating mask data with "1" set for a bit corresponding to each bit in the area to be replaced, and (iii) a mask expansion process for taking out only an area whose bit value is 1 out of the data thus shifted to write the area onto the data read from a register or data with each bit filled with 0. For instance, the rightmost end of input data is shifted up to No. h bit and the data in the register or part of the data with all bits being 0 is replaced in an area LEN in width from No. h bit of the data thus shifted to obtain output data. The area to be replaced at this time is designated by the mask data. Data 32 bits wide will mainly described in the specification. Although the data 32 bits wide is not restrictive, the least significant bit (LSB) and the most significant bit (MSB) are situated at the rightmost and leftmost ends, respectively. In this case, the most significant bit is defined as No. 0 bit, whereas the least significant bit is defined as No. 31 bit.
With respect to a mask data generating circuit utilizable for the generation of mask data in both of the aforementioned cases, what is shown in FIG. 18 may be considered. This circuit comprises a subtracter SUB, two mask bit generating logic circuits MLOG1, MLOG2, and an AND circuit AND. The subtracter SUB generates a bit position at the leftmost end of an area to be extracted or replaced from data LEND representing area width LEN and data h indicating a bit position h on the lower side of the area width. The mask bit generating logic circuit MLOG1 generates data filled with 1 from the leftmost end of the area up to the least significant bit, whereas the mask bit generating logic circuit MLOG2 generates data filled with 1 from the rightmost end of the area up to the most significant bit. The AND circuit AND generates the mask data utilized for mask execution and sign expansion by ANDing these data. There is shown in FIG. 18 an exemplary process of generating mask data for the deposit instruction. The mask data for the extract instruction is generated by replacing No. h bit with No. 31 bit.